Semiconductor memory devices, including flash memory, and controllers thereof typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Memory is a non-volatile data storage device that can be electrically erased and reprogrammed. More generally, non-volatile memory (e.g., flash memory, as well as other types of non-volatile memory implemented using any of a variety of technologies) retains stored information even without power, as opposed to volatile memory, which requires power to maintain the stored information.
The semiconductor memory devices may be configured to include one or more die. Each die may be organized into one or more planes. Each plane may be a two dimensional grid composed of rows (bitlines) and columns (wordlines) that connect to the memory cells. The individual rows that make up the grid may be referred as a page. Common page sizes may include 2K, 4K, 8K, or 16K.
The semiconductor memory devices may be configured to conduct a 4K random read which involves sensing (e.g., reading) each plane with a different random page. In this configuration, each plane can be representative of an independent die, thereby increasing the system parallelism for plane reads.
Some constraints may exist for the semiconductor device to conduct independent plane reads. For example, while two planes are simultaneously sensing, there may be interference between the two planes, which may cause a high bit error rate (BER) or an unwanted spike in peak power. The increase in BER may potentially limit asynchronous independent plane read (aIPR) usage for system (e.g., read exception handling, read threshold calibration) or increase the burden on storage device engineers to meet system BER requirements. The spike in peak power may cause an undesired increase in system load, requiring the system to limit the number of die working in parallel to ensure certain power requirements. To address these issues, the semiconductor device may be configured to conduct synchronous independent plane reads, where each plane is read individually and synchronized based on a common clock signal. However, the semiconductor device may suffer from reduced performance speeds due to each plane having to wait a set predetermined amount of time for a preceding plane to completely finish a sensing operation before conducting a new sensing operation. Therefore, there is a need for an improved semiconductor devices and controllers for said semiconductor devices configured for independent plane reads with improved performance speeds while also limiting bit error rate and managing peak power and average power.